This invention is directed to a scheme of connecting two or more metal levels in a semiconductor package by a via connection. Specifically, this invention is directed to packaging schemes employing multiple level wiring. Such multiple level wiring patterns may exist at the chip (wafer level) or on a wafer carrier having multilevel conductors and interconnections from one level to another.
An example of a prior art multilevel conductor interconnection system is illustrated in IBM TDB Vol. 23, No. 10, pp. 4751-4752 (March 1981).
As disclosed therein, on a substrate surface circuit elements are placed. The device is then sequentially built up by providing a resist layer followed by patterning of the recess for contact holes (vias). The holes are then created and the next layer, a first metal is then patterned. Alignment between the vias and the metal layer is critical.
Processing then continues then by applying a second resist layer and patterning that layer to provide for additional vias. These via must align with the previously defined via in the lower resist layer. Patterning of the second metal layer proceeds and then the steps continue to define a third resist layer. Consequently, as illustrated in this typical prior art scheme, each resist layer is separately patterned. Additionally, each metal layer lying on top of a respective resist layer must be separately patterned. Given the number of patterning steps, production costs for such a device are high. Moreover, a common source of defects which contributes to yield losses deals with the misalignment between vias at various levels. Thus, for example, as illustrated in TDB, the via existing between the top metal and of the circuit element comprises three segments. A misalignment in the patterning to create the holes for any of those segments can result in defective formation of a via. In extreme cases of misalignment an internal short-circuit may result, rendering the entire package unusable.
While the problem of creating aligned vias with a minimum number of steps has been defined relative to multilayer packaging for circuit elements, the same problem exists relative to internal metallization of the device elements themselves. That is, separate metallization for each individual stage. To date, only by exact pattern alignment can yield losses be minimized. Consequently, techniques exist to increase production capacity, the art has been unable to provide a solution which provides the required accuracy yet, at the same time, reduces overall manufacturing costs.
Contemporary packaging schemes employ four discrete levels of metal and seven masking steps with interconnection between levels are required. Consequently, there exists a need in the technology to find the scheme which reduces the number of masking steps while maintaing accuracy.
A second problem related to prior art techniques of sequential patterning and etching is that of contamination which may exist at any individual level. In order to remove contaminants which may be trapped within the package as the vias and metal layers are successively defined, elaborate precautions are employed to reduce the possibility of entrapment of contaminants. This in turn contributes to the overall increase in manufacturing cost.